NB=BANK2, NR=ROW11, NC=COL8
SDRAMC Configuration Register
| NC | Number of Column Bits 0 (COL8): 8 column bits 1 (COL9): 9 column bits 2 (COL10): 10 column bits 3 (COL11): 11 column bits |
| NR | Number of Row Bits 0 (ROW11): 11 row bits 1 (ROW12): 12 row bits 2 (ROW13): 13 row bits |
| NB | Number of Banks 0 (BANK2): 2 banks 1 (BANK4): 4 banks |
| CAS | CAS Latency 1 (LATENCY1): 1 cycle CAS latency 2 (LATENCY2): 2 cycle CAS latency 3 (LATENCY3): 3 cycle CAS latency |
| DBW | Data Bus Width |
| TWR | Write Recovery Delay |
| TRC_TRFC | Row Cycle Delay and Row Refresh Cycle |
| TRP | Row Precharge Delay |
| TRCD | Row to Column Delay |
| TRAS | Active to Precharge Delay |
| TXSR | Exit Self Refresh to Active Delay |